The present invention relates to a method of manufacturing a CMOS thin film semiconductor device of the type used for a thin film transistor (TFT) type liquid crystal display (LCD), and to a CMOS thin film semiconductor device manufactured thereby.
In TFT-LCDs, a polycrystalline silicon (p-Si) TFT which is formed on a quartz substrate, or an amorphous silicon (a-Si) TFT which is formed on a large size glass substrate, is mostly used. The TFTs in the TFT-LCDs are used in one instance for a TFT matrix in a display portion and in another instance for formation of an outer circumferential circuit on a common substrate for driving such a TFT matrix. In the former instance, an n channel TFT is used, and in the latter instance, a CMOS TFT semiconductor circuit is used for achieving high speed operation.
In order to produce a CMOS TFT semiconductor circuit, it is necessary to form an n channel TFT in which an n type dopant is doped and a p channel TFT in which a p type dopant is doped. A method of forming such CMOS TFT semiconductor circuit is fundamentally based on manufacturing processes of an LSI semiconductor device. Namely, the doping treatments are performed in separate processes while alternatively protecting an n type dopant and a p type dopant with masks.
A conventional method will be explained with reference to FIGS. 9A through 9D which illustrate subject matter disclosed by H. Ohshima et al. "Full-Color LCDs with Completely Integrated Drivers Utilizing Low-Temperature Poly-Si TFTs" in Conference Record of Society for Information Display, pp387-390(1993).
FIG. 9A relates to process (a) and shows a cross sectional view of a coplanar type TFT forming a base body. A backing film 2 consisting of SiO.sub.2 is formed on a glass substrate 1. An active layer silicon film 3 is formed on the backing film 2 and the crystalline quality of the active layer silicon film 3 is improved, such as by laser crystallization and thermal crystallization. On the active layer silicon film 3 a gate insulation film 4 consisting of SiO.sub.2 is formed. Further, a gate electrode 5 consisting of a metal or silicon film, for example is formed on the gate insulation film 4 and is processed so as to work as a gate.
In process (b) shown in FIG. 9B, a dope mask 7b is formed for the TFT on the p channel side and a phosphorus ion beam 8 is irradiated onto the TFT on the n channel side to form a source-drain layer 3a. For the irradiation by the phosphorus ion beam 8, an ion doping method suitable for a large scale substrate which performs no mass separation is used instead of using an ion injector as customary used in an LSI manufacturing process. An acceleration voltage of about 100 keV for the phosphorous ion beam irradiation is necessary because the phosphorous ions have to be accelerated to penetrate through the gate insulation 5. With such high acceleration voltage, ion energy is increased and the temperature of the substrate is raised because of a poor thermal conductivity of the glass. For this reason a heat resistant material, such as polyimide, is used for the dope mask 7b, but further measures for reducing the thermal load are necessary, such as by reducing the ion density and by prolonging the doping time.
In process (c) as shown in FIG. 9C, a dope mask 7a is formed on the TFT on the n channel side and a boron ion beam 6 is irradiated onto the TFT on the p channel side to form a source-drain layer 3b.
In process (d) as shown in FIG. 9D, the source-drain layers 3a and 3b are activated, such as by heat treatment and laser beam heating. Further, a protective insulation layer 9 consisting of SiO.sub.2, for example is formed, and after forming contact holes, source-drain electrodes 10 are formed to complate the element. By connecting the source-drains of the p and n channel TFTs as illustrated, an inverter constituting a base unit of a circuit element is formed.